Ownership of a product generation portfolio within the Server Business Unit with responsibility for driving execution from planning through high volume production and end of life. Build tight working relationship with customers and partners to best define products based on their evolving needs. Collaborating with engineering, business development and sales teams to synthe

Lead and manage a talented post silicon team focused on client SOC power management delivering efficient system power management solutions for new APU/CPU client products Lead client SOC power management enablement and validation strategies from pre silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams Proacti

Work with AMD's architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develo p new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing

Create strong links and relationships between AMD and Partner consumer marketing and Alliance teams Build links within regional marketing to enable strong relationships in region Develop and manage WW co marketing funds and program terms; Communicate strategies and fund guidelines to regions and own WW plan roll ups Partner with HP on executing global and regional co mark

Work with AMD's architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develop new groundbreaking AMD technologies Participating in new ASIC and hardware bring ups Debugging/fix existing iss

Work closely with the hardware and firmware team to verifiy Graphics pipeline functionality and performance Part of the verification team to identify areas to improve for power and performance for GPU and APU products Understand and analyze the interactions of hardware and firmware, programming models and applications Requirements Expertise in ASIC digital circuit design

Working on Adaptive Clock Generators for CPU and GPU applications, custom mixed signal circuits and logic design in advanced CMOS technologies using custom and semi custom physical design flows Develop and Simulate RTL code in Verilog Design and Simulate Power Management Circuit Architectures on System level, RTL level and on Transistor level using Matlab, SystemVerilog,

Define product features and capabilities, close architecture, and micro architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all feat

The primary responsibility is for server firmware test case development in conjunction with coordination with architects, BIOS developers, vendors, and quality assurance teams to develop robust, innovative server firmware testing for customer reference boards. A successful candidate will employ solid software testing methodologies, debug capabilities, test case reviews an

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD

Creates and enables efficient geographically agnostic processes and tools to optimize quality and consistency of Cadence CAD designs. Proactively explores, pathfinds, and supports state of the art Cadence PCB design and EDA tools and processes to support our internal teams Capable of debugging and solving technical Cadence PCB design and working directly with Cadence for

An in depth knowledge of the following is required Transmission line theory and microwave engineering concepts such as S parameter, impedance, SSN, etc. System level timing analysis considering effects from silicon IO, package, and board. State of the art PCB stack up/construction. In depth knowledge of AC/DC power delivery, power integrity analysis. Expertise in modeling

Lead the design and implementation of SEV SNP live migration for Linux. Identifying bottlenecks and optimizations & features to advantage EPYC CPUs. Drive features and functionality to our partner technical teams including the Linux kernel, virtualization, and security communities. Support the solutions offered by our partner companies. Review code, build unit tests, and

Enable C++ based diagnostics to be run as patterns on Automated Test Equipment (ATE) Run and debug simulations based on these patterns for hardware developed in Verilog Debug waveforms in Verdi Run emulation on FPGA platforms for these patterns Collaborate closely with design and diagnostics teams to understand and adapt C++ diagnostic algorithms for effective ATE testing

Develop an actionable long term strategy for data center management tools and the related APIs for systems that will deploy AMD Instinct GPUs Lead requirements analysis by deeply understanding partner and customer needs for deployment, management and monitoring large GPU enabled clusters at scale Work closely with AMD engineering teams to leverage internal technical insig